Design of Energy Efficient Logarithmic Approximate Multiplier

In this paper, an efficient logarithm approximate multiplier architecture is proposed. The proposed architecture is designed based on the Mitchell approximate multiplier. Several novel design methods are proposed to make the multiplier more energy efficient while maintaining acceptable computation accuracy. In order to improve the efficiency of the computation, the operands are truncated and the right shifter in the logarithm-to-binary converter is removed in the proposed design. While iterative method is used to compensate for approximation errors, approximate adder is used during error compensation to reduce the complexity of the compensation circuit. A novel error metric is also proposed to evaluate the accumulated error effects of approximate multipliers in real applications. Compared with the conventional Mitchell approximate multiplier, the proposed design can achieve a 56.1% smaller delay, a 23.9% smaller area and a 65.9% smaller power-delay product (PDP) while its approximation error is reduced. Case studies of image processing and K-means clustering are used to verify the effectiveness of the proposed design.