An Efficient Accelerator on FPGA for Large Convolution and Correlation using Winograd

FPGAs have become an attractive option for deep learning algorithms acceleration due to their reconfigurability and abundant logic resources. However, facing large kernel convolution and feature correlation, FPGA-based accelerators are often limited by on-chip DSP resources, making it difficult to cope with the exponentially increased computational load. To break through the limitation, we design the Winograd Accelerator Cores (WACs) to achieve efficient computation of convolution and correlation at the same time. To meet the bandwidth requirements of WACs with less FPGA resources, we propose an on-chip buffer system based on Line-Buffer and sliding registers. To maximize the usage of FPGA resources for computing while ensuring the scalability of accelerators on different FPGA devices, we propose a dataflow-driven multi-core accelerator architecture based on WACs. Finally, we implemented the accelerator using Xilinx Vivado HLS and deployed it on FPGA devices for performance evaluation to demonstrate the efficiency. On Xilinx xczu9eg, the actual performance can reach 1078.73GOPS, and the DSP utilization radio reaches 4.21. Its performance is more than 37.83% higher than that of Angel-Eye, and the DSP utilization ratio is 158.40% and 12.60% higher than that of Angel-Eye and Extended-DPU, respectively.