An Improved Test Structure of Boundary Scan Designed for 2.5D Integration

While chiplet provides more IC design opportunities, 2.5D advanced heterogeneous integration brings more challenges to test due to its complex structure and interconnection. This paper proposes an improved test structure of boundary scan aiming at the interconnection in different directions between 2.5D stacked chiplets. By segmenting the boundary scan chain inside each chiplet and make each segment configurable, we test interconnections in different directions between chiplets at the same time, with shorter test vector and smaller area compared to ieee 1149.1. Additionally, a new configuration method based on the standard TAP state machine is suggested in order to shorten the configuration time for interconnection testing. The total test vector in the scenario of three core interconnect testing is lowered by 76.58% compared to the standard one, additionally cutting the configuration time by 82.76% when compared to employing user-defined instructions reserved in the standard. The area is 10.65% smaller than the typical testing structure.