A 12-bits 100 MSPS Current-Steering DAC With Low-Power In 40nm CMOS

This paper presents the design and investigation of a 12-bit high-precision low-power digital-to-analog converter (DAC) based on TSMC 40nm CMOS technology. The proposed DAC architecture is a current-steering type, which employs a 5 most significant bits (MSBs), 4 middle LSBs (MLSBs), and 3 least significant bits (LSBs) decoding segments, operating at a sampling rate of 100 million samples per second (MSPS). The overall circuitry comprises reference circuits, switch driving circuits, decoding circuits, and current source arrays. The performance of the DAC circuitry is evaluated through the simulation of static and dynamic error indicators using Cadence Spectre. The simulation results indicate that the proposed DAC exhibits excellent static performance with differential non-linearity (DNL) of ±0.12 LSB and integral non-linearity (INL) of ±0.18 LSB. Additionally, the DAC demonstrates low static power consumption of approximately 9.7 mW. The dynamic performance of the DAC is evaluated in terms of effective number of bits (ENOB) and spurious-free dynamic range (SFDR), which are estimated to be 11.92 bits and 81 decibels of carrier (dBc) at 100 MHz, respectively.