UVM-based Reusable Hardware Accelerator Verification Platform

We design a UVM-based reusable hardware accelerator verification platform to better verify increasingly complex hardware accelerator designs. The verification platform mainly uses coverage-driven convergence technology, combined with directional testing and constrained random excitation, to perform functional verification on the IP in the multi-core accelerator chip. The verification environment is built according to the verification requirements of the convolutional neural network hardware accelerator, and the data flow control functions such as convolution, activation, pooling, and fully connected function layers in the design and the base address and data offset are verified. Verify existing hardware accelerator, the experimental results prove that the verification platform quantifies the verification progress according to the mechanism in UVM to ensure the verification completeness of the functional modules; In addition, the accelerator verification platform of the network model of different structural layers can be reused with a small amount of modification, which shortens the verification cycle.