Low Voltage and Low Power PLL with Current-Reuse Oscillator

In this paper, a low voltage and low power charge pump PLL based on current-reuse LC oscillator is designed. Different from the traditional differential LC VCO, the VCO in this design uses the cross-coupled pair of PMOS and NMOS to achieve the effect of Current-Reuse. The phase noise of the VCO is not affected by the second harmonic term of the common source node. In order to further reduce power consumption, the design uses 0.8V low voltage power supply and all the MOSFETs adopt a low threshold structure. The simulation results show that the power consumption of the whole circuit is 1.2mW and the phase noise at 1MHz frequency offset is -109dBc/Hz when the PLL output is 1.8GHz under the TSMC 180nm process and 0.8V supply voltage. The whole PLL can achieve integer frequency division of 1.68GHz $\sim 1.92$ GHz, and the locking time is less than 10us.