Investigation of Trap Evolution of Hf0.5Zr0.5O2 FeFET During Endurance Fatigue by Gate Leakage Current

In this work, we study trap evolution in TiN/Hf0.5Zr0.5O2/interlayer/Si FeFET during endurance fatigue by the gate leakage current. We fabricated the FeFET devices with different interlayers (SiO2 or SiON) and measured gate leakage during endurance fatigue. We model the gate leakage current by considering direct tunneling (DT), Fowler–Nordheim tunneling (FNT), and trap-assisted tunneling (TAT) mechanisms. The experimental and simulation results are well agreed. The leakage current in FeFET is mainly determined by traps in the interlayer, due to the TAT mechanism and high electric field across the interlayer enhanced by polarization charges of the ferroelectric layer. The trap generation in the interlayer occurs during endurance and this induces the increase of leakage current. However, the trap at the ferroelectric/interlayer interface is not increased during the endurance fatigue. Less charge trapping and trap generation appears in FeFET with the SiON interlayer compared with the SiO2 sample. This is due to a higher energy level and lower density of traps in the SiON interlayer based on the leakage current simulation and first-principles calculations. Our work provides a perspective for the endurance mechanism in FeFET and is helpful to device design.