Comprehensive TCAD-Based Retention Study of Thyristor RAM (TRAM) for Low-Power and High-Speed Cryogenic Memory Applications

A capacitor-less 1-T dynamic random access memory (DRAM) cell based on a thin capacitively coupled thyristor (TRAM) is analyzed across a wide temperature range from 300 K down to 77 K through comprehensive Technology Computer-Aided Design (TCAD) simulations for large capacity, high-speed, and low-voltage cryogenic cache memory applications. Different data-loss mechanisms, including Shockley-Read-Hall (SRH) generation/recombination, band-to-band generation, and junction leakage, are accounted for retention time analysis. Data retention behavior is elucidated for different base doping via energy band diagram and electrostatic potential distribution along the p+-n-p-n+ channel. As base-doping increases, data 1 retention time decreases due to higher recombination of carriers, and data 0 retention time increases due to increased barrier height leading to lower diffusion of carriers. Utilizing the narrow bandgap of Germanium, a Ge-TRAM is proposed for lowering the operating voltage to 0.75 V to compensate for the cooling power cost overhead while operating at 77 K. Data 1 and 0 retention time exceeds 105 s at 77 K because of lower SRH generation/recombination and carrier’s lack of thermal energy. However, Ge-TRAM requires higher base doping for successful data retention to prevent junction leakage due to lower barrier heights.