Spice-Compatible Modeling of Double Barrier MTJ for Highly Reliable Circuits

This paper proposes a compact model of tungsten (W) engineered perpendicular magnetic tunnel junction (p-MTJ) with double CoFeB/MgO interfaces for circuit design. Reliability issues, such as process variation and stochastic switching, have been considered to enhance the accuracy of the model, rendering it approaching the reality application scenarios. A STT-MRAM memory circuit is simulated by using this model to investigate the writing and reading performance. With the benefits brought by W to p-MTJ, the circuit demonstrates less writing energy and higher reading reliability, owing to the enhanced perpendicular anisotropy and high tunnel magneto resistance ratio.