Domain Wall-Magnetic Tunnel Junction Analog Content Addressable Memory Using Current and Projected Data

With the rise in in-memory computing architectures to reduce the compute-memory bottleneck, a new bottleneck is present between analog and digital conversion. Analog content-addressable memories (ACAM) are being recently studied for in-memory computing to efficiently convert between analog and digital signals. Magnetic memory elements such as magnetic tunnel junctions (MTJs) could be useful for ACAM due to their low read/write energy and high endurance, but MTJs are usually restricted to digital values. The spin orbit torque-driven domain wall-magnetic tunnel junction (DW-MTJ) has been recently shown to have multi-bit function. Here, an ACAM circuit is studied that uses two domain wall-magnetic tunnel junctions (DW-MTJs) as the analog storage elements. Prototype DW-MTJ data is input into the magnetic ACAM (MACAM) circuit simulation, showing ternary CAM function. Device-circuit co-design is carried out, showing that 8-10 weight bits are achievable, and that designing asymmetrical spacing of the available DW positions in the device leads to evenly spaced ACAM search bounds. Analyzing available spin orbit torque materials shows platinum provides the largest MACAM search bound while still allowing spin orbit torque domain wall motion, and that the circuit is optimized with minimized MTJ resistance, minimized spin orbit torque material resistance, and maximized tunnel magnetoresistance. These results show the feasibility of using DW-MTJs for MACAM and provide design parameters.

I. Introduction

As Data size increases and Moore's law slows down, alternative in-memory computing (IMC) architectures are being studied and used to efficiently process information. Conventional analog IMC often uses crossbar array architectures and nonvolatile memory (NVM) such as resistive random-access memory (RRAM) and has shown many applications in neural network acceleration [1], [2], [3], neuromorphic computing [4], statistical learning [5], signal processing [6], [7], scientific computing [8], [9], and other fields. However, there is a challenge extending these architectures to operations other than matrix dot multiplication. Existing IMC architectures rely on extensive analog to digital conversion (ADC) and digital to analog conversion (DAC) to switch between matrix multiplication and other computations such as activation functions [10]. The consequent conversion cost greatly dilutes efficiency in both power and speed; e.g., data converters can consume around 85% of the total energy in a typical RRAM-based neural network accelerator [11]. This energy overhead is especially critical for edge computing.