Split Inductor Design Considerations for Split-Phase Three-Phase Inverter

Two-Level Split-Phase (2L-SP) topology has emerged as a promising candidate for Wide Band Gap (WBG)-based Two-Level (2L) three-phase inverters. 2L-SP comprises P and N-cells whose mid-points are connected through split inductors. Compared with standard 2L, 2L-SP provides better immunity to crosstalk, lower switching loss, and conducted EMI emissions, which is favorable for WBG devices. However, these performance metrics depend on the value of split inductance. Further, split inductors experience a current spike during the switching transition. Although increasing split inductance is shown to improve the metrics and suppress the current spikes, an approach for optimal selection of split inductance is yet to be devised. This paper presents an analysis for design considerations, based on current spikes, for split inductor sizing. At first, a simplified model is derived and validated on a 75 kVA SiC-based hardware prototype. This is followed by an analysis of proposed model in the context of split inductor sizing.