Evaluation of Current-Limiting Strategies for Grid-Forming Inverters

Grid-forming (GFM) inverters are likely to play a significant role in future power systems, however the extent of their impact depends on how effectively they can limit fault current to prevent damage while still supporting the grid. This paper presents a novel GFM control architecture that combines an inner single-loop voltage control with an outer proportional-integral-derivative (PID) based dynamic threshold virtual impedance (DTVI) current limiting control in parallel to the GFM control. Notably, in contrast to standard (proportional) threshold virtual impedance (TVI), the PID-based DTVI achieves asymptotic current tracking. Moreover, by removing the inner current loop this architecture increases the achievable control bandwidth of the GFM control. The paper compares current limiting performance of DTVI implemented in the synchronous reference frame (DTVI-dq0), DTVI implemented in the natural reference frame (DTVI-abc), and current reference saturation implemented in the synchronous reference frame. Both DTVI strategies are used in conjunction with a single-loop voltage control architecture implemented in the synchronous reference frame while the current reference saturation strategy is embedded within a traditional cascaded loop control architecture (outer voltage loop and inner current loop) also implemented in the synchronous reference frame. Experimental results are provided comparing the performance of these strategies under three-phase, single line-to-line, and single line-to-neutral faults using an 83 kVA, 850 Vdc, 277/480 Vac GFM inverter operated as both a standard three-leg and as a four-leg inverter. The results demonstrate that the proposed architecture can asymptotically track current limits with less than 1/2 cycle overshoot and effectively limit currents on a per-phase basis while retaining voltage control and maintaining sinusoidal waveforms during asymmetrical faults.