Design of an Optical Receiver for Multi-core Optical Fiber

This paper presents an optical receiver designed to match multiple core optical fiber, implemented in a 0.18
$\mu\mathrm{m}$
CMOS process. The chip consists of a photodiode (PD) array and transimpedance (TIA) circuits, including the TIA core, Bandgap (BG) and Bias. The placement of PD array is highly matched with the multiple core optical fiber and each PD is followed by a TIA. The TIA achieves a 60 dB ohm transimpedance gain with a 200 MHz bandwidth and the input reference current noise is
$7.2 \text{pA} / \sqrt{ } \text{Hz}$
. The BG can stably output a 1.2 V voltage and shows a good stability in the post simulation under 128 process corners. The Bias can provide the current required to drive TIA through a mirror transistor. Eye diagrams are shown when operating at bit rates of 200 M bps and 300 M bps with a forward input reference voltage of 1.2 V. While achieving high transmission efficiency, the chip area is only
$0.78\times 0.92$
mm2 which allows for more compact designs and suit for a wide range of application scenarios.