SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor

As the size and complexity of System-on-Chip (SoC) continue to grow, product performance and durability requirements have also become a vital part of chip design. By deploying monitors and structures built into the silicon design, we can obtain real-time data on the performance of the chip, which in turn can be used to study the health of the silicon and predict its degradation. This is a particularly important requirement for safety-critical applications such as automotive. In this paper, a case study of Path Margin Monitor (PMM) is presented as part of an automotive SoC subsystem that can monitor the functional paths of silicon in real-time throughout the entire silicon lifecycle.