A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation

Chip-Iet based multi-die 3DIC design methodology is the paradigm shift in semiconductor manufacturing that enables scalable design integration for SysMoore era. Stacking multiple heterogeneous dies in a single stack opens chip design to a world of unexplored challenges. One such challenge is testing of the individual dies and the integrated complex stack to improve DPM. The IEEE 1838 standard defines 3DIC DFT architectures for individual dies and stack level test. In this paper we present a case study on an industrial design to leverage EDA tools and flows to implement IEEE 1838 compliant DFT architectures for full die and integrated stack.