GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications

Edge signal processors have difficulty balancing the high throughput and high dynamic range (HDR) requirements of modern digital signal processing (DSP) such as digital beamforming (DBF) and pulse compression due to size, weight and power (SWaP) constraints. Compute-in-Memory (CIM) has proven to be an energy-efficient and high-throughput solution, reducing the data transfer on the bus. However, as shown in Fig. 1, when applied in DSP, the previous CIM macros face new challenges: 1) general-purpose floating-point (FP) CIMs based on logic gates require long pipeline delays[1], [2], artificial intelligence (AI) FP CIMs based on mantissa pre-alignment cannot handle HDR data due to quantization loss in pre-alignment[3-5], 2) integer-based analog CIMs require large readout bit widths to satisfy the signal-to-noise ratio (SNR) of DSPs, resulting in larger power consumption and area[6], [7], 3) CIMs for real matrix require six rounds of sequential operations to achieve complex matrix multiplication in DSP, resulting in significant data storage and transfer overhead.