Packaging of a 25-Tiles Device on Large Dimension AlN Ceramic Substrate Keeping Low Dead Areas and Tight Planarity

Chiplet architecture technologies, in addition to expanding computing resources, is also applicable to high-resolution optical sensors development, meeting low dead areas and good planarity on the whole focal plane. While choosing a monolithic solution soon leads to yield issues, we explored a packaging solution with 25 chips butted in an array on a ceramic substrate. Many challenges were addressed: first, minimizing the distance between chips, in order to keep a constant pitch on a chip and in between chips; second, controlling the bonding position of each chip to ensure a good planarity on the whole focal plane. In addition, a specific design work was provided to ensure a good signal integrity on the ceramic package. Finally, temperature modelisations were made to optimize the design of the ceramic package and extract correctly the heat on the backface.