Scalable Time Measurement System based on a Multi-FPGA Architecture

Many modern applications in various scientific, industrial, and consumer sectors, such as Time-of-Flight Positron Emission Tomography and 3D imaging scanning in medicine, or Particle Identification in nuclear physics, require the measurement of time intervals with both high-precision (picoseconds) and extremely large number of channels (hundreds). Among the most established Time Interval Meters (TIMs), Time-to-Digital Converters (TDCs) are increasingly a very popular choice, especially thanks to their extremely high flexibility, in the version implemented in Field Programmable Gate Array (FPGA) devices. However, the number of channels is becoming so high in the most advanced applications, that a single FPGA device is not sufficient to host the necessary architecture and therefore the problem arises of realizing a multi-FPGA based TDCs, necessarily all perfectly synchronized with each other. Given the picoseconds-precision required, the problem of TDCs synchronization is a very significant issue that requires the development of methodologies and techniques designed and developed ad hoc. The proposed solution is a structure that meets these needs and is implemented using a "main board" that hosts a 16-nm Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156 Multi-Processor System-on-Chip (MPSoC). The main board coordinates up to 8 FPGA-based "satellite boards", each hosting a Xilinx 28-nm 7-Series Kintex-7 XC7K410T-2FFG676I FPGA, in which a 16-channel, 12-picoseconds precision FPGA-based TDC is implemented. In this way, it is possible to manage up to 128 channels with a precision of 12 ps r.m.s. The satellite boards are connected to the main board via the Aurora protocol on Gigabit Transceiver Hardmacro (GTH), making it possible to achieve a data collection rate of 250 Msps by the main board. The entire system is housed in a 4U, 460 x 305 mm, 4U rack.