SET and SEU Hardened Clock Gating Cell

Clock gating is a common approach for reduction of dynamic power consumption in digital designs. It is achieved by insertion of special clock gating cells in the circuit, enabling to switch off the clock signal to selected flip-flops. However, as the clock gating cell is composed of a latch and a logic gate, it may be affected by the Single Event Upsets (SEUs) and the Single Event Transients (SETs) in radiation environment such as space. Given that a single clock gating cell may be connected to many flip-flops, a fault in one clock gating cell may lead to the circuit or system malfunction. Therefore, solutions for SET and SEU mitigation in clock gating cells are necessary for rad-hard designs. This work introduces two clock gating cell designs based on the use of a delay element and a guard gate to filter input SETs, and triple modular redundancy (TMR) to mitigate SEUs. The TMR concept can also provide enhanced immunity to permanent errors. The proposed designs have been optimized to minimize the number of transistors and improve the SET robustness of internal nodes.