A Model For Probabilistic Fault Propagation with the Approach of Effective Fanouts in the Logic Circuits

In today's world, the discussion of component failure in engineering systems is the main challenge in new complex system design because the simultaneous failures in multiple components can degrade the performance of the system. The common motivation and goal of most of the work done in the field of digital circuit reliability are to achieve accurate reliability while providing an efficient method of dealing with the faults in larger circuits. Achieving accurate reliability requires considering several problems, the most important of which are the consideration of convergent paths and the problem of masking error, which play an essential role in the accuracy of calculations This paper presents a novel method for the reliability analysis of logic circuits based on probabilistic computation. This approach introduces a fault propagation matrix, signal probabilities matrix, and effective fanouts to handle the reconverge fanouts and masking error problems. Various simulations have illustrated the accuracy and scalability of the proposed method on the ISCAS 85 benchmark circuit. The results have shown a less than 1 % average error for reliability estimation.