Development of an Efficient and Reliable Verification Technique for Complex SoC Package

As System-on-chip (SoC) continues to develop and become more complex, robust verification procedures are required to guarantee adequate functionality and performance of the SoC. The verification of SoC packages using formal connectivity checks is covered in detail in this work. The traditional verification techniques frequently fall short in ensuring complete connectivity and error-free operation because SoCs comprise a variety of functional blocks, communication interfaces, and complicated interconnections. This study presents a method for thoroughly validating the connection within the SoC package using formal verification techniques. Our research shows that the formal connectivity check that has been proposed greatly improves the verification coverage, leading to a greater level of design reliability and a shorter time to market for SoC products. Our study makes a positive impact on the field of verification by providing a methodical and reliable way to guarantee error-free connectivity within complex SoC packages. AFI tool is used to perform formal verification of connectivity check and results show that all the SoC pins are mapped correctly to the package pins. The time taken to perform formal verification after the script is developed is 0.03sec