A Novel Approach to Braun Multiplier Design Utilizing High-Speed Parallel Prefix Adder for Low Power Applications

This project develops an innovative Braun Multiplier design to address power consumption and chip area challenges. Integrating a high-speed parallel prefix adder enhances computational speed by leveraging parallel processing capabilities. The synergy between the Braun Multiplier and the adder yields a solution optimizing performance, power efficiency, and chip area usage. Meticulous design and engineering yield notable improvements in power efficiency and chip area utilization. The project drives advancements in digital circuit design and optimization methodologies, achieving a 16% area reduction and 18.2% lower power consumption via the FS-GDI technique, while achieving full-swing output voltage, distinguishing it from GDI and M-GDI techniques.