Physical Design Implementation of SoC Module with Performance Optimization

As the demand for higher performance and lower power consumption in Integrated Circuits (ICs) increases, the need for efficient and effective routing techniques also grows. Channel density routing and filler cell insertion are two such techniques that aim to optimize the use of available routing resources in ICs, thereby improving the overall performance and reliability of the design. Channel density routing is a technique that involves adjusting the spacing between adjacent routing tracks in order to increase the density of routing channels in a given area. This technique is particularly useful for designs with limited routing resources and for reducing routing congestion in critical areas of the IC. Critical factors in SoC physical design include power consumption, area utilization and timing constraints. Achieving power efficiency is paramount, necessitating careful transistor sizing, voltage scaling and the use of low-power design techniques. Effective area management is crucial to optimize chip size and reduce manufacturing costs, often involving Floorplanning and Placement strategies. This work carried out in three stages. At stage1 Efficient Redistribution (RDL) layer routing enabled the reduction of effective resistance to 57.67 % in the Hard Macro instances. By channel density optimization method area reduction of 7.5 % is observed in this design. In the stage2 timing closure ensures that signals propagate within specified limits, requiring the careful adjustment of clock trees, signal routing and the use of advanced optimization tools. The Setup and Hold time checks are reported as -337 ps & -449 ps. At last stage3 Physical Verification (PV) checks ensures that the design is ready for signoff stage.