Electrical Properties of Each Channels in Vertical Stacked Gate-All-Around Nanosheet s-Si pMOSFETs

SiGe was utilized as the source and drain material to enhance the performance of Nanosheet pGAAFETs. Furthermore, the number of stacked nanosheets affects the stress on each nanosheet. This paper uses TCAD to simulate varied strains of each nanosheet of 3-stacked NSFETs with certain Ge content. After high-k metal gate (HKMG) processing, the bottom Si layer of 3-stacked NSFETs experienced the greatest stress, while the top layer experienced the least amount of stress. As the number of stacked nanosheets increases, the stress on the nanosheets decreases, leading to a decrease in $I_{dsat}$ enhancement.