Hardware Implementation of Block Ciphers – A Case Study on Encrypted Image Transfer Over Universal Asynchronous Receiver Transmitter

Communication protocols such as Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), Inter-Integrated Circuits (I2C), and Computer Area Networks (CAN) exist to facilitate communication among devices. This work studies a comparison of the additional overhead of offering Advanced Encryption Standard (AES)-128 and PRESENT-64 algorithms with reconfigurable UART on the transmitter and receiver side to offer data encryption. Advanced Encryption Standard (AES) in the basic loop architecture and PRESENT in the fully unrolled architecture for their implementation in the proposed study of secured data transfer over the UART channel. AES-128 consumes almost three times more clock cycles to encrypt and decrypt than PRESENT-64. Considering that AES-128 takes only double the input size of PRESENT-64 and requires thrice the number of clock cycles, AES-128 is more time-consuming. Xilinx Field Programmable Gate Array (FPGA) implementation results suggest that PRESENT-64 consumes slightly more onboard resources than AES-128 since the proposed work employs an unrolled PRESENT architecture. The complete architecture is specified using Verilog HDL and implemented in Xilinx families, namely Artix7, Spartan6, Virtex6, and Virtex7 series of FPGAs.