Integration of a Full Wavelet-Based Image Compression System on a Field-Programmable Gate Array

The increasing significance of having an efficient compression method for raw images before transmission or storage stems from their substantial storage requirements on computer hard drives. The proposed method for compressing images necessitated the implementation of a hardware design pipeline to execute a two-dimensional Distributed Arithmetic (DA) for the Discrete Wavelet Transform (DWT). Before conducting the conventional two-dimensional discrete wavelet transform (DWT) on the input image, the Distributed Arithmetic (DA) technique employs a lookup table (LUT) based FPGA architecture to construct a filter bank devoid of multipliers. In image compression, utilizing Differential Pulse-Code Modulation (DPCM) involves the computation of the Discrete Wavelet Transform (DWT) and the corresponding wavelet coefficients. The Huffman encoder, constructed by amalgamating the least probable symbols, is then provided with the modified image for compression. The efficacy of the revised DA-based wavelet is assessed by using a Simulink model before its implementation. In the context of this approach, the code is implemented using the Verilog programming language. The proposed methodology evaluates the traditional approach concerning adders, multipliers, internal memory capacity, computation time, power consumption, image dimensions, and hardware efficacy.