A 6.7–3.6-pJ/b 0.63–7.5-Gb/s Rapid On/Off Clock and Data Recovery With <55-ns Turn-On Time

In this letter, we present a rapid on/off 0.63–7.5-Gb/s digital clock and data recovery with a low-turn-on time and recovered clock jitter. The clock and data recovery (CDR) employs a fast-on 1.875–3.75-GHz digitally controlled oscillator followed by a
$2\times $
integer-N PLL. The DCO incorporates an 8-bit digitally controlled phase interpolator embedded in a
$6\times $
–
$12\times $
injection-locked clock multiplier for fast turn-on and low-output jitter. DCO’s output is filtered using the fast-on PLL while generating the sampling clock phases for the half-rate CDR. Fabricated in the TSMC 65-nm process, the CDR recovers the clock with
$\rm < $
1.3-ps RMS jitter while dissipating 26.6 mW at 7.5 Gb/s and 14.4 mW at 3.75 Gb/s. Duty cycling the CDR operation lowers the average data rates to 0.63 Gb/s with less than 55-ns turn-on time and 1.6-
$\rm \mu {\mathrm{ s}}$
on/off period.