Reducing Power Dissipation in Memory Repair for High Fault Rates

Nanometric scaling steadily increases failure rates, which are particularly acute for ultimate complementary metal–oxide–semiconductor (CMOS) and post-CMOS devices. We previously established an ECC-based method of memory repair that dramatically reduced the cost for high fault rates, and in this article, we establish a repair architecture that further reduces the power cost. Since CAMs are power hungry (as the address of each memory operation is compared with all the tag fields), we use a cache with the following innovations: 1) innovative repair architecture: although a direct-mapped cache and a set-associative cache that employs offset address bits are efficient for performance of CPUs, we show that they are inefficient for memory repair, since the characteristics of the memory words that need to be replaced in memory repair are different from the case of CPUs, and hence, rather than using any of these cache architectures, we establish an innovative memory repair method that uses another cache and an overflow block; 2) this architecture is thousand times more efficient than other approaches to memory repair based on a CAM or cache; 3) we present a yield computation that determines the size of each block of this repair architecture that is needed to achieve any target yield, and we establish this using a novel probabilistic approach, mathematical approaches and algorithms; and 4) at high fault rates, the yield computation is intractable; we make it tractable via an innovative recursive mathematical approach that significantly reduces the number of operations.