Study of Error Amplifiers for Low Power Capacitorless Low Dropout Voltage Regulator using 110 nm CMOS Technology

Capacitorless low dropout (CLDO) voltage regulators are becoming a key power management sub-block in contemporary electronic circuits. However, a high quiescent current in a CLDO regulator drains more power from the system and rapidly reduces the battery charge. Therefore, this study aims to identify the effect of different error amplifier topologies on the quiescent current of a low-power 110 nm CLDO regulator by simulating two CLDO regulators which utilize telescopic and two-stage error amplifier architectures operating at a nominal input voltage of 1.2 V and regulating an output voltage of 1.0 V with maximum load up to 50 mA. The obtained results show that both CLDO regulators are able to achieve single-digit micro-range quiescent current with the telescopic-base CLDO having better quiescent current of 4.81 µA compared to the two-stage-base CLDO quiescent current of 5.18 µA. However, the two-stage-base CLDO regulator demonstrates better overall performance in terms of better accuracy, stability and noise rejection although has a slightly higher quiescent current.