Performance Analysis of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET with Punchthrough Stop Layer

In this paper, 14nm Silicon-On-Insulator-based Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness (EOT) of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across the fin’s thickness. The results show that the I
on
=101.5µA/µm and I
on
/I
off
is 3.2x10
⁷
, DIBL=25.3 mV/V and Subthreshold Swing (SS) = 63.88 mV/dec are obtained. Thus, the Gaussian Channel-based FinFET architecture can provide optimum results for Junctionless-based FinFET devices. Further, to limit the parasitic leakage current in SOI-based FinFETs, possible solutions such as the Punch-Through Stop layer are also examined in this work, and about 36.8% of leakage current is reduced.