Implementation of a Tile-Grained Pipeline Architecture for CNN Accelerator

In this paper, we propose a pipelined neural network accelerator circuit. The accelerator consists of two 256MACs PE arrays, operates at a frequency of 250MHz, and achieves a theoretical throughput of 256GOPS while utilizing relatively fewer FPGA resources. We implement the hardware on the Xilinx Zynq UltraScale+ MPSoC ZCU102 platform. Experimental results demonstrate that using this architecture can reduce DRAM access by nearly 40%.