An Enhanced Load Regulation LDO with Ripple Cancellation for Clock Generator in 28nm CMOS

This paper presents a structure that effectively mitigates load ripples generated by a voltage-controlled oscillator (VCO) attached as a load to a low-dropout (LDO) regulator. This employs the suggested sub-pass transistor and reduced load capacitor. This method effectively reduces ripples while maintaining a steady power supply. Furthermore, by reducing the load capacitor within the LDO regulator, this design solves space constraints. The proposed structure is composed of the integration of the voltage controlled delay line (VCDL) and sub-pass transistors. The proposed LDO regulator is manufactured using 28nm CMOS technology and regulates a 1.2V supply to 1V. The measured improvement in terms of ripple reduction amounts to 46 %.