An Exploration of the Effective Path for Current Conduction in a Triple Gate Junctionless FinFET

The goal of this work is to exclusively investigate the effective path for current conduction in the channel of a Triple Gate (TG) Silicon-ON-Insulator (SOI) Junctionless Fin Field Effect Transistor (JLFinFET). It is observed that various structural parameters play a key role in deciding the location of the effective current path both in full depletion mode and partial depletion mode in TG SOI JLFinFET. Considering the present day technology requirements 20 nm was chosen as the gate length. Simulations performed using 3-D TCAD namely ATLAS by Silvaco Inc. reveal that the conducting path from source to drain starts from nearer to the centre of the channel (i.e, at half the fin height and half the fin width) when the transistor switches from the OFF state to the ON state. It is also observed that when the triple gate transistor scales down in size the capacitive coupling between the top gate and side gates is a crucial factor in determining the location of the effective current path.