Low Power Gate Voltage Controlled Schmitt Trigger with Adjustable Hysteresis and 0.1Vth Margin in 22nm FDSOI

This paper introduces a Schmitt trigger with ad-justable hysteresis, specifically developed for low power per-formance and fabricated using 22nm FDSOI technology. The proposed design incorporates a dynamic threshold voltage gen-eration technique to achieve both reduced power consumption and high noise immunity. The voltage-controlled hysteresis is adjustable to enable the design to be customized for different applications. The Schmitt trigger is implemented using a stan-dard CMOS process and the circuit performance is analyzed using Cadence Virtuoso simulation. The outcome presents that the suggested design achieves a low power consumption ranging from nW to pW and a high noise immunity with an adjustable hysteresis of 0 V to 0.4V to both gate voltages. The suggested design is well-suited for low power requirements in various digital circuit applications, including memory, microprocessors, and sensors.