Implementation of Chua’s Transmitter and Receiver in 45nm CMOS Technology for Secure Communication

In recent years, there has been a growing interest in utilizing chaos for secure communication due to its inherent properties of sensitivity to initial conditions, non-linearity, and unpredictability. However, implementing chaos-based systems on FPGA platforms has power consumption and size limitations. By leveraging the advanced capabilities of 45nm CMOS technology in the Cadence tool, we aim to achieve efficient power management and compact circuit layout, enabling a successful migration from FPGA to the 45nm CMOS process. The study seeks to showcase the practicality and advantages of this shift, offering valuable knowledge for forthcoming projects in low-power design. The proposed implementation aims to improve communication systems’ efficiency, reliability, and security with a power consumption of 5mW and device size of 50 μm × 50 μm. By successfully transitioning chaos from FPGA to CMOS, this research enhances secure communication systems by enabling low-power and compact implementations. The results of this work have the potential to impact various fields, including wireless communication, the Internet of Things (IoT), and wearable devices.