Next Generation Gate-all-around Device Design for Continued Scaling Beyond 2 nm Logic

We explore GAA transistor design elements for performance scaling beyond 2nm technology node. We examine the various resistance components of a 1
^st
generation GAA FEOL transistor with typical 2nm node design rules. We propose different schemes to reduce each resistance component of the GAA transistor to improve its drive-current and circuit performance. Using our calibrated process, device and ring-oscillator modeling platform, we evaluate the device and circuit performance impact of each of these schemes. We show that the drive-current and circuit performance of GAA transistors can be improved by over 50% and 18%, respectively, which aligns with the performance scaling requirements for logic nodes beyond 2nm.