Accelerating supersingular isogeny Diffie-Hellman (SIDH) cryptosystem for the security of resource-constrained IoT devices with FPGA

It is imperative to note that post-quantum cryptography, such as supersingular isogeny Diffie-Hellman (SIDH), is essential for ensuring that Internet of Things (IoT) devices have a restricted amount of resources. The primary challenges in assuring the security of IoT devices are addressed by this work's analysis of SIDH implementations designed for field programmable gate array (FPGA) architecture. Extensive efforts towards implementing the architecture for a rapid and constant-time FPGA implementation of SIDH. This quantum-resistant cryptographic primitive is a crucial component for adhering to NIST's PQC standardization. Our goal with this paper is to demonstrate how FPGA architectures can enhance the parallelism of SIDH, making it a more practical option for securing resource-limited IoT devices. Our focus is on providing a reliable speed record for SIDH, which is crucial for ensuring the security of IoT devices. The design for isogeny computation was built over p434 in Xilinx Virtex 6 and produced 45ms for public key generation in addition to 35ms for secret key generation.