The Design of a High-Throughput Hardware Architecture for the AES-GCM Algorithm

This paper proposes the hardware architecture capable of processing the AES-GCM algorithm in parallel and pipeline. To boost the hardware efficiency, two parallel AES processing units, each consisting of a mixed inner- and outer-round pipelining architecture, are employed in the encryption/decryption module. These two AES units share a key expansion unit to save the hardware resource. To optimize the architecture of the AES algorithm, the S-box function is directly realized with the built-in BRAM in the FPGA technique to decrease the number of LUTs used, and implemented with the composite field operation in the ASIC technique in order to save up to 25% logic gates. In the GHASH module design, two pipelining finite field GF
$(2^{128})$
multipliers with appropriate data scheduling are utilized. In addition, realizing the finite field multiplication with the Karatsuba algorithm can further save 50.7% of hardware resource. The resulting AES-GCM IP has been implemented and verified with a Xilinx Virtex 5 series device (XC5VLX220), and a tsmc 0.18-
$\mu \text{m}$
cell library. In FPGA verification, the working frequency can achieve 223.314 MHz, yielding the maximum throughputs of 57.17 Gbps. The number of slices/BRAMs used is 5,944/109. The resulting ASIC can operate at 197.239 MHz in simulation and achieve a high throughput of 50.49 Gbps. The core area of the chip is
$6,552\,\,\mu \text{m}\,\, \times 6,516 \, \mu \text{m}$
. The power consumption is 1,466.5 mW.