Edge Computing Convolution Operator Hardware Design for Satellite Payload

Processing large image sizes on satellite payload poses challenges due to limited computing resources and on-chip memory constraints. The transfer of data from off-chip memory to initiate numerous convolution operations for edge computing object detection incurs significant time and power consumption. This paper proposes a new architecture in Field Programmable Gate Array (FPGA) and utilizes Direct Memory Access (DMA) to access off-chip memory, thereby reducing the power consumption and data transfer time. The implementation result shows low power consumption and reduced computation time.