Modeling and Analysis of Simultaneous Switching Noise for Full Wafer Scale Chip Core

In this paper, we model and analyze the simultaneous switching noise (SSN) for the full wafer scale chip (FWSC) core. The FWSC has emerged as a potential solution in the artificial intelligence (AI) accelerator market with its high performance and power efficiency. However, the enormous switching operations of FWSC result in a huge simultaneous switching current (SSC), which leads to a high SSN and degrades the power integrity (PI) in the FWSC. Therefore, the SSN should be accurately evaluated to guarantee the PI in the FWSC. We model and analyze the SSN within the hierarchical FWSC core PDN comprising voltage regulator modules (VRMs), PCB PDN, multiarray power/ground (P/G) silicone rubber socket-based PDN, and chip PDN. The hierarchical FWSC core PDN is modeled into equivalent circuit models, and the SSC spectrum of the FWSC core is extracted by a chip power model (CPM), respectively. Then, we fully analyze SSN in the time domain using both the modeled PDN impedance and SSC spectrum. As a result, the high SSN corresponding to 66 % of VDD is induced by overlapping of the impedance peak of PDN and the current peak of SSC spectrum.