Signal and Power Integrity Design of Advanced Interface Bus (AIB) for FPGA Packages

Advanced Interface Bus (AIB) is a die-to-die interface that connects chiplets or tiles of different functions in a single package through organic package substrate (AIB-O) or Silicon-based Embedded Multi-die Interconnect Bridge (EMIB). In Intel heterogeneous SiP (System in Package) products, AIB is widely used to connect the peripheral dies and the FPGA logic die for flexibilities of tile reuse and integration of different process nodes. Comparing to the monolithic package integration, the challenges with interconnecting different dies through AIB while keeping performance and power close to what would be possible with monolithic solution need to be addressed. These challenges include crosstalk, multi-reflection, power delivery noise, hence the reduced timing margin. In this paper, we investigated the signal integrity, power integrity and architecture optimization of AIB-O. With the proposed novel clocking scheme and power sharing strategies, as well as the trade-off of horizontal/vertical cross talk through optimized bump planning, and effective removal of pessimism in channel jitter, we were able to make the system margin sufficient to enable our new product solutions that meet the cost and performance targets.