D-Band Flip-Chip Packaging with Wafer-Level Cu-pillar Bumps

The transmission loss of a Cu pillar microstrip-microstrip transition in a flip-chip package is characterized. The used components are fabricated in the back-end layers of a standard BiCMOS process, with Cu pillars deposited on top as the flipped die and UBM coating on pad as the substrate. Four variations with different pitches and openings on the ground plane are all characterized and compared using both measurement and FEM simulation. It is found that a small pitch with a de-coupling aperture are the keys to minimize the transition losses. The de-embedded insertion loss of a single Cu-pillar transition is between 0.3-0.5 dB over 110-170 GHz (D-band). Such a wafer-level bumping approach greatly improves the throughput and uniformity, and meanwhile, demonstrates comparable transition losses with other flip-chip packages using similar sized bumps.