Interfacing Synchronous Modules to Multi-Clock Synchronous Digital Systems Implemented in FPGA

Nowadays, digital circuits lead to low-power consumption, high performance, reuse, etc. These circuits are typically synthesized in the synchronous paradigm, where the global clock signal is responsible for state transitions. They can be implemented in Deep-Sub-Micron (MOS-DSM) technology, in the case Very Large-Scale Integration (VLSI) or Field Programmable Gate Array (FPGA). The synchronous digital design implemented in VLSI_DSM or FPGA is hampered by the global clock signal that makes it challenging to meet these requirements. One solution is to treat the system as a set of modules operating with multiple clocks. In this paper, we propose three new asynchronous interfaces of wrapper type, which perform data communication between such modules efficiently and satisfying the elasticity property of the module. The wrapper application is intended for multi-point systems; in this case, modules with up to two inputs or up to two outputs, but not both. A comparison is realized with communication ports used in literature GALS systems, which shows an average reduction of 41.0% and 48.5%, respectively, in the number of LUTS (Look-Up-Tables) and latency.