Physical Implementation of Multi Power Domain SoC Design

Most System on Chip (SoC) designs have multiple blocks in it which operate at different voltages, by operating different blocks of the same SoC at different voltages great amount of power saving can be done. Also, there is a direct relationship between Dynamic power and supply voltage (V
dd
) (dynamic power is proportional to ${\text{V}}_{{\text{dd}}}^2$). So, if some blocks of SoC can operate at low voltage, the power consumption reduction will happen and lead to better design power performance. But whenever this Multi power domain approach is followed it adds complexity to Floor planning and Power planning to avoid this complexity the framework proposed in the paper can be adopted for Place and Route (P&R) which helps in doing efficient Floorplanning, Power planning and power saving.