Low Power CMOS LNA For Wireless Implantable Neural Stimulators

This research paper introduces a low-power, low-voltage CMOS low-noise amplifier (LNA) that operates at sub-milliwatt levels. The LNA incorporates a rejection filter designed to protect the receiver from ultra-wideband signal of high-power intensity. The proposed LNA topology combines inductive interstage matching and input/output matching to achieve low-power operation at ultra-low-voltage of 0.75 V. The implementation of circuit is done using 180 nm CMOS technology. Noise figure of less than 0.45 dB is obtained at 2.4 GHz carrier frequency. The outcomes of the simulation also yielded significant findings which shows a 12.71 dB gain, Sll of less than - 11.15 dB, and S22 of -10.83 dB. Furthermore, the stability factor S is greater than 1 and the reverse isolation S12 is -16.85 dB. The power consumption of the LNA in this work is remarkably low, measuring only 805 uW when supplied with a voltage of 0.75 V.