Front-End Design of 64-Bit Carry Look Ahead Adder

This work utilizes Verilog hardware description language (HDL) and field-programmable gate array (FPGA) technologies to develop a high-performance 64-bit carry look ahead adder (CLA). The proposed CLA architecture is optimized for speed and area efficiency, incorporating an efficient carry look-ahead generator (CLG) circuit to minimize propagation delay. The design is implemented on an FPGA board and evaluated for parameters such as power consumption, area utilization, and timing constraints. The results demonstrate superior performance compared to existing designs, with a maximum operating delay of 13.746ns and power usage only up-to 1.08mW. The improved CLA architecture finds applications in digital signal processing (DSP), image and video processing, and high-speed computing.