Algorithm and Processor Architecture for the Implementation of the Minimum Filtering Technique in Complex-Valued CNNs

In this paper, we present a resource-efficient algorithmic solution regarding the fully parallel hardware implementation of the basic filtering operation performed in the complex-valued convolutional neural networks (CNNs). In fact, this basic operation computes the inner products of adjacent complex-valued vectors formed by a sliding time window from the current data stream with the impulse response vector of a 3-tap finite impulse response (FIR) filter. We adapt Winograd's minimal filtering algorithm for a case of the complex-valued data and applied it to develop a fully parallel hardware-oriented algorithm for implementing basic filtering operations in complex-valued CNNs. We also additionally apply the well-known Gauss's trick for multiplying complex numbers, which replaces 4 multiplications and 2 real additions with real 3 multiplications and 3 real additions. A general view of the architecture of the processor unit for the implementation of this operation is also given. A fully parallel hardware implementation of the proposed processor unit provides 50% savings in the number of embedded multipliers compared to a fully parallel hardware implementation of the naive calculation method.