A Design of Source-Switched Charge Pump Circuit with 65nm Technology by using Bayesian Optimization

A charge pump (CP) has been one of the most widely used components in many phase-lock loops (PLLs), and new topologies of the CP have been created a lot these days to optimize certain variables. This paper presents a method for designing CP circuits and applying the AI algorithm to optimize power consumption of the CP. The study proposes using the Bayesian optimization (BO) algorithm to design and optimize the source-switched CP circuit. In this work, the width and length variables of each transistor in the CP circuit were found by the BO algorithm to reduce the power consumption of the circuit. After being optimized, the power consumption parameter was lowered by 73.6%, from 2.58mW to 0.67mW. Although the power consumption of the circuit fell significantly, it was not the global minimum of the power consumption of the source-switched CP circuit. Thus, further research would be required to find the global minimal power consumption of the source-switched CP circuit and improve other parameters of the CP circuit, such as jitter and performance.