A Memory-Saving Approach for 5G New Radio Low-Density Parity-Check Decoders

This paper presents a memory efficient design for a Low-Density Parity-Check (LDPC) decoder. The design is based on a combination of two techniques that consists of (i) the proposed Enhanced single minimum Min-Sum (EsmMS) algorithm for check-node update processing, which requires only the first minimum value among variable-to-check input messages and its index instead of two minima, and (ii) the memory split method, which adapts to the varying check-node degree of 5G LDPC codes. The implementation results on Xilinx Kintex UltraScale+ (xcku5p) FPGA show that the proposed decoder requires 37% less storage space than MS-based decoders, provides a decoding throughput of 2.63 Gbps, while yielding a decoding gain up to 0.32 dB at the BER of 10
⁻⁸
compared to the Min-Sum decoder.