Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs

FPGAs have high computation capabilities that can overload the memory subsystem and harm system performance. This paper proposes runtime resource management techniques that consider system limitations, such as the available compute resources and the memory bandwidth. By orchestrating the acceleration tasks in a heterogeneous multitenant FPGA operating system, we enhance the system's performance. The proposed approaches isolate the parallel running acceleration services in time and memory space domains based on their memory access behavior to reduce DRAM organization and access pattern effects. The proposed schedulers are evaluated and implemented on a Zynq UltraScale+ FPGA board running both acceleration and software tasks. The evaluation shows (on average) improvements in memory read/write throughput (10%), task execution time (30%), and makespan time (29%) over an existing greedy FPGA scheduler.